SPACE TILE ARCHITECTURE

One interface.
Your capability.

Add FPGA processing, acceleration or memory to the common spacecraft architecture. Evaluate the tile, carrier and software together against the mission’s constraints.

01MODULAR HARDWARE

Space Tiles

Astria and Galaxia provide FPGA options. Additional processing and memory tiles remain in development.

02DEVELOPMENT RESOURCES

Go deeper into the hardware.

Reference designs and documentation from the original Adiuvo product sources. Follow the source for current availability.

ADIUVO5

Astria® Tile

A 59 mm by 59 mm Spartan 7 tile for integrating FPGA capability without designing a chip-down solution.

Product resources
ADIUVO7

Galaxia® Tile

A Galaxia tile using the same FPGA as the development board for mission design-in, advanced prototyping, and testing.

Product resources

Source: Adiuvo Engineering. Specifications should be confirmed for the chosen mission configuration.

NEXT MISSION. NEW POSSIBILITIES.

What are you
building for orbit?

Bring us your mission constraints.
Let’s engineer the compute around them.

Discuss your mission