Development board

Galaxia® Space Development Board

Space development board for demanding space applications requiring low power, high performance, and low single-event upset rate.

Technical specifications available

Galaxia® Space Development Board hardware
Specifications describe the product architecture. Availability, radiation configuration, performance and qualification evidence are confirmed during mission review. DANU product flight heritage is not claimed.

Board provisions

Galaxia® Space Development BoardBoard provisions
Provided featureCertus™-NX LFD2NX-40
Provided feature80 I/O accessible via PMOD
Provided feature14 ADC channels including ADC reference
Provided feature128 Mbit NOR flash for configuration
Provided feature256 Kbit MRAM memory
Provided feature100 MHz oscillator
Provided featureLattice in-system programmable hardware management expander
Provided featureRPi Pico

FPGA details

Galaxia® Space Development BoardFPGA details
LUTs40K
BRAM2.5 Mbit
DSP56
ADCs / OscillatorsTwo ADCs and inbuilt 32 KHz and 450 MHz oscillators

Positioning

Galaxia® Space Development BoardPositioning
Equivalent device noteCommercial equivalent of the Certus-NX-RT device offered by CAES

RISC-V

Galaxia® Space Development BoardRISC-V
Processor deployment noteRISC-V processors can be deployed on this development board using the Lattice Propel tool

Unique RPi Pico capability

Galaxia® Space Development BoardUnique RPi Pico capability
CapabilityClock generation up to 65 MHz reference clock using the PIO
CapabilityCommunications emulation of a differential backplane bus
CapabilityCommunications monitoring and logging
CapabilitySensor emulation across the system and implementation of failure modes
CapabilityComplex communications creation: implementation of a SpaceWire communication protocol between the FPGA and the Pico
CapabilityPower management and monitoring of the power network and dissipated power under load or beam-line testing

Application

  • Deployment Cameras
  • Temperature Control Systems
  • Motor and Actuator Control
  • Telemetry and Telecommand processing
  • Health and Usage Monitoring
  • Radiation Beam Testing for design proving
  • Implementing Compression algorithms
  • Implementing Cryptographic security

Unique RPi Pico capability

  • Clock Generation — Generation of up to 65 MHz reference clock using the PIO.
  • Communications emulation — Emulation of a differential backplane bus.
  • Communications Monitoring — Monitoring and logging communications.
  • Sensor emulation — Emulation of sensors across the system and implementation of failure modes.
  • Complex communications creation — Implementation of a SpaceWire communication protocol between the FPGA and the Pico, providing a simple interface controlled over USB communication.
  • Power management and monitoring — Monitoring the power network to control, monitor, and observe dissipated power under load or test conditions such as a beam line.

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