Development board
Astria Board
Development board pairing a Spartan-7 FPGA with a Raspberry Pi RP2040 for logic, embedded-system, and image-processing development.
Technical specifications available
Specifications describe the product architecture. Availability, radiation configuration, performance and qualification evidence are confirmed during mission review. DANU product flight heritage is not claimed.
Key features
| Feature | AMD Spartan 7 XC7S6 with 6,000 logic cells, 5 BRAM, 2 CMT, 10 DSP48 |
|---|---|
| Feature | Raspberry PI RP2040 processor with dual-core Arm Cortex-M0+ running at 133 MHz |
| Feature | FTDI232H for JTAG programming |
| Feature | SDRAM: 64 Mbit |
| Feature | 4 PMODs - three for FPGA and one for RPi 2040 |
| Feature | Ability to fit high-speed LVDS transceiver on one FPGA PMOD |
| Feature | User Flash connected to FPGA: 32 Mbit QSPI |
| Feature | FPGA Configuration PROM: 256 Mbit |
| Feature | Four user LEDs |
| Feature | Four push button switches |
| Feature | Four SPST switches |
| Feature | 100 MHz reference clock |
References
| Public repository | Reference designs, XDC, schematics, and Vivado board definition are listed in a public Bitbucket repository |
|---|
Reference design / example
- RPI_FPGA_UART_AXI — Vivado 2023.2 example: UART in RP2040 communicates with FPGA; protocol over UART accesses AXI peripherals; includes AXI GPIO and AXI timer/PWM demo with LEDs and slide switches.
- SDRAM — Vivado 2023.2 SDRAM example for the SDRAM on the board.
- MBV_MCS — Vivado & Vitis 2024.1 MicroBlaze V (RISC-V) MicroController System implemented on the Spartan 7.
- S7_LEO — Vivado 2023.2 I/O check of all FPGA PMOD I/O and 4 LEDs; walks an LED around all 28 LEDs (4 on board, 24 on PMOD LED not included); also connects through the user flash to the RPi for testing.
- DELTA_SIGMA — Vivado 2024.1 delta-sigma output at 1 KHz on PMOD 1 pin 1 and PWM sine output at 1 KHz on PMOD 1 pin 2; external RC needed for recovery.
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